This application claims the priority benefit of Taiwan application serial no. 89108111, filed Apr. 28, 2000.
1. Field of the Invention
The invention relates in general to a method of fabricating a thin-film transistor (TFT). More particularly, this invention relates to a method of fabricating a thin-film transistor using four photomasks. In addition to the applications of fax machine, contact image sensor (CIS) such as a scanner and various electronic devices, this method can also applied to fabrication of thin-film transistor flat panel display such as liquid crystal display (LCD) and organic light-emitting diode (OLED).
2. Description of the Related Art
A thin-film transistor flat panel display basically comprises a thin-film transistor device and a flat panel display device. The thin-film transistor device further comprises more than one thin-film transistor arranged as an array. Each thin-film transistor corresponds to one pixel electrode. The thin-film transistors are formed with the stack of a gate, a gate dielectric layer, a channel layer and a source/drain region stacked on an insulation substrate. The thin-film transistors in the thin-film transistor flat panel display are normally used as switching devices.
In FIG. 1A, an insulation substrate 100 is provided. A conductive layer is sputtered on the insulation substrate 100. The conductive layer of a single or multiple layers (such as a composite layer) is made of at least one type or multiple types of metal or alloy thereof. The metal or the alloy of these metals is selected from aluminum, copper, gold, silver, molybdenum, chromium, titanium, tungsten, wherein the aluminum alloy further includes neodymium Nd). As an example, the conductive layer includes at least a titanium/aluminum/titanium composite layer (not shown), and the alloy thereof, wherein the aluminum alloy may further include neodymium. Using a first photolithography and etching process, the chromium/aluminum composite layer is patterned as a gate 110 and a gate line.
In FIG. 1B, a silicon nitride layer (SiNx) 120, a hydrogenated amorphous silicon layer (a-Si:H) 130 and a doped amorphous silicon layer (n+ a-Si) 140 are formed in sequence on the insulation substrate 100. A second photolithography and etching step is performed to pattern the doped amorphous silicon layer 140 and the hydrogenated amorphous silicon layer 130. As shown in FIG. 1B, the patterned doped amorphous silicon layer 140 and the doped hydrogenated amorphous silicon layer 130 are aligned over the gate 110.
In FIG. 1C, a conductive layer is sputtered on the insulation substrate 100. The conductive layer of a single or multiple layers (such as a composite layer) is made of at least one type or multiple types of metal or alloy thereof. The metal or the alloy of these metals is selected from aluminum, copper, gold silver, molybdenum, chromium, titanium, tungsten, wherein the aluminum alloy further includes neodymium (Nd). As an example, the conductive layer includes at least a titanium/aluminum/titanium composite layer (not shown), and the alloy thereof, wherein the aluminum alloy can further include neodymium. A third photolithography and etching step is performed to form a doped amorphous silicon layer 140, a source/drain line 150a, a source/drain metal layer 150 and a source/drain region 140a. 
In FIG. 1D, a silicon nitride protection layer 160 is formed over the insulation substrate 100. A fourth photolithography and etching step is performed to form an opening 166 in the silicon nitride protection layer 160. The opening 166 exposes a portion of the source/drain metal layer 150.
In FIG. 1E, an indium tin oxide layer (ITO) 170 is sputtered over the substrate 100. A fifth photolithography and etching step is performed to form a pixel electrode 170.
As mentioned above, the conventional method requires five photolithography and etching steps to form the thin-film transistor. For each photolithography and etching step, processes such as dehydration bake, priming, photoresist coating, soft bake, exposure, post-back of exposure, development, hard back and etching are performed. Thus, each additional photolithography and etching step greatly increases the fabrication cost. Furthermore, the yield of products decreases as they undergo each additional photolithography and etching step.
The invention provides a method of fabricating a thin-film transistor, preferably on an insulation substrate. The method can be applied to fabrication of fax machine, CIS such as scanner and various electronic devices. In addition, the method can also be applied to fabrication of thin-film transistor flat panel display such as liquid crystal display and organic light-emitting diode (OLED).
A first conductive layer, a gate dielectric layer, a silicon layer and a doped silicon layer are formed on an insulation substrate in sequence and patterned to form a gate and a gate line. A second conductive layer is formed over the insulation substrate. The second conductive layer and the doped silicon layer are patterned to form a source/drain line, a source/drain conductive layer and a source/drain region. The source/drain line is located at both sides of the gate line without being connected to the source/drain conductive layer, so as to avoid a short circuit caused by any contact between the source/drain line and the gate and the gate line. A protection layer is formed and patterned over the insulation substrate so that openings are formed on the source/drain conductive layer and the source/drain line at both sides of the gate line. A transparent conductive layer is formed over the insulation substrate. The transparent conductive layer is patterned to form a pixel electrode, and a portion of the remaining transparent conductive layer electrically connects the source/drain line at both sides of the gate line with the source/drain conductive layer.
Thus constructed, only one photolithography and etching step is required for patterning the doped silicon layer to form the gate and gate line. Another photolithography and etching step is required for forming the source/drain line, the source/drain conductive layer and the source/drain region. Therefore, the steps of photolithography and etching are reduced from five to four. Consequently, the fabrication cost is decreased and the yield of the product is enhanced.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.